The present invention relates to an electrically programmable non-volatile semiconductor memory device having an electrode called a booster plate.
An EEPROM having an electrode called a booster plate is described, for example, in 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 238-239 (I. D. Choi, D. J. Kim, D. S. Jang, J. Kim, H. S. Kim, W. C. Shin, S. T. Ahn, and O. H. Kwon, Samsung Electronics Co., LTD.).
In this specification, the electrode called xe2x80x9cbooster platexe2x80x9d is referred to as xe2x80x9cbooster electrode.xe2x80x9d An EEPROM cell having the booster electrode will now be generally described.
FIG. 1A is a plan view of a conventional memory cell, FIG. 1B is a cross-sectional view taken along line Bxe2x80x94B in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line Cxe2x80x94C in FIG. 1A. For simple description, bit lines and an underlying interlayer insulating film are omitted in FIG. 1A.
As is shown in FIGS. 1A to 1C, device isolation insulation films 102 are formed in a surface portion of a P-type silicon substrate 101. Device regions 103 are defined on a surface of the substrate 101 by the device isolation insulation films 102.
A tunnel insulation film 104, a floating gate 105, an insulation film 106 and a word line 107 are successively formed on the device region 103. A structure wherein the floating gate 105 and word line 107 are stacked is called a stacked-gate structure.
Reference numeral 108 denotes a gate of a select transistor. N-type diffusion layers 109, 110 and 111 are formed in the device region 103. The diffusion layer 109 is connected to a source line (not shown), and the diffusion layer 110 is to a bit line 112. The number of diffusion layers 111 is two or more and these layers 111 function as source/drain regions of memory cell transistors, respectively.
A booster electrode insulating film 114 is formed over the periphery of the stacked-gate structure and the diffusion layers 111. A booster electrode 115 is formed on the insulating film 114. Reference numeral 144 denotes an interlayer insulation film.
FIG. 2A shows an equivalent circuit of the conventional EEPROM. For the purpose of simple description, FIG. 2A shows the case where two word lines (WL1, WL2) and two bit lines (BL1, BL2) are provided.
As is shown in FIG. 2A, a select transistor ST11, cell transistors MC11 and MC21 and a select transistor ST21 are connected in series between a bit line BL1 and a source line SL.
Similarly, a select transistor ST12, cell transistors MC12 and MC22 and a select transistor ST22 are connected in series between a bit line BL2 and the source line SL.
A word line WL1 is commonly connected to the gates of the cell transistors MC11 and MC12, and a word line WL2 is commonly connected to the gates of the cell transistors MC21 and MC22.
A drain-side select gate line SG1 is commonly connected to the gates of the select transistors ST11 and ST12, and a source-side select gate line SG2 is commonly connected to the gates of the select transistors ST21 and ST22. A back-gate (BULK) of each transistor is common.
In the NAND type EEPROM, the potential of the back-gate BULK is varied in accordance with the operation mode. A booster electrode BP is capacitively coupled to the mutual connection nodes and floating gates FG11, FG12, FG21 and FG22 of the respective transistors.
The write operation will now be described on the basis of the disclosure in the above-mentioned document. In the following description, a write operation for injecting electrons into the floating gate is called xe2x80x9c0xe2x80x9d write, and a write operation for injecting no electrons into the floating gate is called xe2x80x9c1xe2x80x9d write. FIG. 2B shows potentials of respective nodes in the write mode.
In the NAND type flash EEPROM disclosed in the above-mentioned document, the potential of the selected word line WL1 is set at 13 V, the potential of the booster electrode BP is at 13 V, the potential of the bit line BL1 designated for xe2x80x9c0xe2x80x9d write is at 0 V, the potential of the drain-side select gate line SG1 is at 3.3 V, the potential of the source-side select gate line SG2 is at 0 V, and the potential of the non-selected word line WL2 is at 3.3 V.
At this time, the potentials of both the write-selected word line WL1 and booster electrode BP are 13 V. A potential corresponding to about a coupling ratio (xcex3 pgm) xe2x80x9c0.78xe2x80x9d between the floating gate FG11 and word line WL1 can be produced at the floating gate FG11 by a potential of the booster electrode BP, and a potential of about 10 V is applied to the tunnel insulation film.
Accordingly, even if the write potential is 13 V, electrons are injected into the floating gate FG11 through the tunnel oxide film having about 10 nm thick. Thus, xe2x80x9c0xe2x80x9d write is effected in the cell MC11.
On the other hand, the gate potential of the cell MC21 belonging to the same bit line BL1 and having the gate connected to the non-selected word line WL2 is 3.3 V, and the potential of the booster electrode BP is 13 V. At this time, the voltage of 3.3 V applied to the word line WL2 acts to lower the potential of the floating gate FG21. Thus, no electrons are injected in the floating gate FG21.
On the other hand, the potential of the bit line BL2 designated for xe2x80x9c1xe2x80x9d write is 3.3 V. Since the potential of the drain-side select gate line SG1 is 3.3 V at this time, the select transistor ST12 is cut off when the potential of xe2x80x9c3.3 V-VthSTxe2x80x9d has been transferred to the N-type diffusion layer. As a result, the region 116 of the diffusion layer 111 shown in FIG. 1B and channel 113 of the memory cell (hereinafter referred to as xe2x80x9cNAND cell channel 116xe2x80x9d or simply xe2x80x9ccell channel 116xe2x80x9d) is set in the floating state.
In this case, xe2x80x9cVthSTxe2x80x9d is a threshold voltage of the select transistor ST12. At this time the potential of the cell channel 116 is raised by the potential of booster electrode BP.
The potential, 13 V, of the selected word line WL1 contributes to raising the potential of cell channel 116 through the floating gate FG12. In this manner the potential of cell channel 116 is raised up to about 8 V.
In the cell MC12 having the gate connected to the selected word line WL1, a potential difference between the channel thereof and the word line WL1 decreases to xe2x80x9c13 Vxe2x88x928 V=5 Vxe2x80x9d and no electrons are injected in the floating gate FG12.
Thus, data xe2x80x9c1xe2x80x9d is written in the cell MC12. As described above, in the EEPROM having the booster electrode BP, the potential of the cell channel 116 is greatly raised up to about 8 V in the write-selected cell MC12 connected to the bit line BL2 designated for xe2x80x9c1xe2x80x9d write.
In addition, in the cell MC22 having the gate connected to the non-selected word line WL2, a potential difference between the channel thereof and the word line WL2 is xe2x80x9c3.3 Vxe2x88x928 V=xe2x88x924.7 Vxe2x80x9d and no electrons are injected in the floating gate FG22.
As has been described above, the main function of the booster electrode BP is to increase the effective coupling ratio xcex3 pgm so that the potential of the floating gate is sufficiently raised at the time of xe2x80x9c0xe2x80x9d write, thereby lowering the potential (write potential VPP) of the selected word line from 17 V to 13 V.
Furthermore, the channel potential of the cell for xe2x80x9c1xe2x80x9d write is raised from xe2x80x9c3.3-VthSTxe2x80x9d, as in the prior art, to about 8 V, thereby making it difficult for electrons to be injected in the floating gate. Thereby, occurrence of xe2x80x9cerroneous writexe2x80x9d, such as erroneous write of xe2x80x9c0xe2x80x9d, can be prevented.
However, in the conventional EEPROM having the booster electrode, the coupling ratio xcex3 pgm in write mode varies due to xe2x80x9cprocessing errorxe2x80x9d at the time of forming the device isolation region 102 and xe2x80x9cprocessing errorxe2x80x9d at the time of forming the floating gate 105, as will be described below in detail.
FIG. 3 is a bird""s eye view showing dimensions of the floating gate.
Suppose, as shown in FIG. 3, that the dimension of the floating gate 105 along the bit line is xe2x80x9caxe2x80x9d, the dimension of floating gate 105 along the word line is xe2x80x9cbxe2x80x9d, the height of floating gate 105 is xe2x80x9ccxe2x80x9d, and the width of the device region 103 is xe2x80x9cdxe2x80x9d.
In addition, suppose that the thickness of the tunnel insulation film 104 between the substrate 101 and floating gate 105, as shown in FIGS. 1A to 1C, is xe2x80x9ctox1xe2x80x9d, the thickness of the insulation film 106 between the floating gate 105 and word line 107 is xe2x80x9ctox2xe2x80x9d, and the thickness of the booster electrode insulating film 114 between the floating gate 105 and booster electrode 115 is xe2x80x9ctox3.xe2x80x9d
At this time, the capacitance C1 between the substrate 101 and floating gate 105 is given by
C1=∈0xc2x7∈r(axc2x7d)/tox1.
The capacitance C2 between the floating gate 105 and word line 107 is given by
C2=⊂0xc2x7∈r(b+2c)a/tox2.
The capacitance C3 between the floating gate 105 and booster electrode 115 is given by
C3=∈0xc2x7∈r(2bxc2x7c)/tox3.
When the potential of word line 107 is write potential VPP, the potential VFG of the floating gate 105 is given by the following, if the charge in the floating gate 105 is ignored:
(VPPxe2x88x92VFG)xc2x7(C2+C3)=VFGxc2x7C1
Accordingly,
VFG=(C2+C3)xc2x7VPP/(C1+C2+C3)=xcex3 pgmxc2x7Vpp.
As the capacitance C2, C3 increases, the potential VFG becomes closer to the potential VPP and increases. At this time, the width xe2x80x9cbxe2x80x9d of floating gate 105 along the word line 107 is not included in the capacitance C1 but is included in the capacitance C2, C3.
Accordingly, as the width xe2x80x9cbxe2x80x9d increases, the capacitance C2, C3 increases and the value of potential VFG also increases. In other words, if the width xe2x80x9cbxe2x80x9d varies, the value of potential VFG varies.
The variance in potential VFG results in a variance in write charge (quality of electrons injected in the floating gate), and the variance in threshold voltage of the cell in which data xe2x80x9c0xe2x80x9d has been written increases.
In particular, in these years, data to be stored in the EEPROM has gradually changed from general two-value data to multi-value data. Thus, there is a demand that the threshold voltage of the cell be distributed in a very narrow range.
In order to meet the demand, the quantity of electrons injected in the floating gate needs to be controlled with higher precision. However, the variance in potential VFG makes the control difficult.
In addition, if the value of potential VFG varies, a possibility increases that electrons may be injected in the floating gate of the non-selected cell in which a gate is the word line or the cell for xe2x80x9c1xe2x80x9d write at the time of data write.
Although the width xe2x80x9cdxe2x80x9d of the device region 103 is not included in the capacitance C2, C3, it is included in the capacitance C1. The effective coupling ratio xcex3 pgm is expressed by
xcex3 pgm=(C2+C3)/(C1+C2+C3)=[{(b+2c)a/tox2}+{(2bxc2x7c)/tox3}]/[{(axc2x7d)/tox1}+{(b+2c)a/ tox2}+{(2bxc2x7c)/tox3}]
Accordingly, if the width xe2x80x9cdxe2x80x9d of device region 103 varies, the coupling ratio xcex3 pgm varies at the time of data write.
FIG. 4 is a graph showing the dependency of the coupling ratio xcex3 pgm upon the width xe2x80x9cdxe2x80x9d of the device region 103. In FIG. 4, the variation of the coupling ratio xcex3 pgm is plotted when the width xe2x80x9cdxe2x80x9d of the device region 103 has varied in the cell having substantially the following values: a=0.25 xcexcm, b=0.45 xcexcm, c=0.1 xcexcm, d=0.25 xcexcm, tox1=10 nm, tox2=14 nm, and tox3=30 nm.
As is shown in FIG. 4, the coupling ratio xcex3 pgm decreases as the width xe2x80x9cdxe2x80x9d of device region 103 increases.
If the coupling ratio xcex3 pgm varies, the variation in distribution of threshold voltage of the cell increases. In order to decrease the variance of distribution of threshold voltage, it is possible, for example, to divide the write pulse into small components and inject electrons into the floating gate little by little. In this case, however, the write time increases.
Furthermore, if there is a cell wherein electrons may be easily injected due to variance in coupling ratio xcex3 pgm, defects such as erroneous write or read disturb (weak write occurring when a voltage is produced between the word line and substrate) may easily occur.
The present invention has been made in consideration of the above circumstances, and the present invention provides a non-volatile semiconductor memory device and a method of manufacturing the same, wherein a variation in potential VFG due to a variation in coupling ratio xcex3pgm can be suppressed, and defects such as erroneous write, in which electrons are erroneously injected in a floating gate of a cell non-selected for write or a cell designated for xe2x80x9c1xe2x80x9d write, or read disturb can be prevented.
According to a first aspect of the invention, there is provided a non-volatile semiconductor memory device comprising:
a device isolation insulation layer, formed on a semiconductor substrate, for defining a device region;
a floating gate formed above the device region and having a pair of first side faces opposed to a side face of the device isolation insulation layer which is located on the device region side;
a control gate formed above the floating gate; and
a booster electrode having faces opposed to a pair of second surfaces of the floating gate which are substantially perpendicular to the pair of first side faces;
wherein a distance between the pair of first side faces of the floating gate is equal or not more than a width of the device region defined by the device isolation insulation layer, and dimensions of the floating gate are determined based on a coupling ratio between the floating gate and the booster electrode.
According to a second aspect of the invention, there is provided the device of the first aspect, further comprising:
a first insulation film formed between the floating gate and the substrate;
a second insulation film formed between the floating gate and the control gate; and
a third insulation film formed between the floating gate and the booster electrode.
According to a third aspect of the invention, there is provided the device of the first aspect, wherein a plurality of stacked gates each having the floating gate and the control gate are formed on the semiconductor substrate, and
the booster electrode is formed between adjacent two of the stacked gates.
According to a fourth aspect of the invention, there is provided the device of the first aspect, further comprising a plug for contact with a bit line, the plug being formed of the same conductive material as the booster electrode.
According to a fifth aspect of the invention, there is provided the device of the first aspect, further comprising a wiring formed of the same conductive material as the booster electrode.
According to a sixth aspect of the invention, there is provided a non-volatile semiconductor memory device comprising:
a device isolation insulation layer, formed on a semiconductor substrate, for defining a device region;
a floating gate formed above the device region and having a pair of first side faces opposed to a side face of the device isolation insulation layer which is located on the device region side;
a control gate formed above the floating gate; and
a booster electrode having faces opposed to a pair of second surfaces of the floating gate which are substantially perpendicular to the pair of first side faces,
wherein a distance between a pair of first side faces of the floating gate is equal or not more than a width of the device region defined by the device isolation insulation layer, and the control gate comprises:
a first conductive film formed above the floating gate; and
a second conductive film formed on the first conductive film and the device isolation insulation film.
According to a seventh aspect of the invention, there is provided the device of the first aspect, further comprising an insulation layer formed on the control gate.
According to an eighth aspect of the invention, there is provided the device of the first aspect, wherein the distance between the pair of first side faces is substantially equal to the width of the device region.
According to a ninth aspect of the invention, there is provided the device of the first aspect, wherein the device isolation insulation layer is formed of an insulation material buried in a trench formed on the semiconductor substrate, the trench being self-aligned with the pair of first side faces of the floating gate.
According to a tenth aspect of the invention, there is provided a non-volatile semiconductor memory device comprising:
a floating gate formed above a semiconductor substrate via a first insulation film;
a control gate opposed to a first face of the floating gate via a second insulation film; and
a booster electrode opposed to a second face of the floating gate via a third insulation film,
wherein a width of the floating gate opposed to the semiconductor substrate via the first insulation film, a width of the floating gate opposed to the control gate via the second insulation film, and a width of the floating gate opposed to the booster electrode via the third insulation film are substantially equal to one another, and dimensions of the floating gate are determined based on a coupling ratio between the floating gate and the booster electrode.
According to an eleventh aspect of the invention, there is provided a non-volatile semiconductor memory device comprising:
a floating gate formed above a semiconductor substrate via a first insulation film;
a control gate opposed to a first face of the floating gate via s second insulation film; and
a booster electrode opposed to a second face of the floating gate via a third insulation film,
wherein a width of the floating gate opposed to the semiconductor substrate via the first insulation film, a width of the floating gate opposed to the control gate via the second insulation film and a width of the floating gate opposed to the booster electrode via the third insulation film are substantially equal to one another; and
a cell array portion, where a plurality of stacked gates in which the floating gate and the control gate are stacked on each other are provided, and the booster electrode is buried between the stacked gates adjacent to each other.
According to a twelfth aspect of the invention, there is provided a non-volatile semiconductor memory device comprising:
a floating gate formed above a semiconductor substrate via a first insulation film;
a control gate opposed to a first face of the floating gate via a second insulation film; and
a booster electrode opposed to a second face of the floating gate via a third insulation film,
wherein a width of the floating gate opposed to the semiconductor substrate via the first insulation film, a width of the floating gate opposed to the control gate via the second insulation film and a width of the floating gate opposed to the booster electrode via the third insulation film are substantially equal to one another, and
the control gate comprises a first portion capacitively coupling with the floating gate via the second insulation film and a second portion for connecting the first portion to another first portion adjacent to the first portion.
According to a thirteenth aspect of the invention, there is provided the device of the sixth aspect, further comprising an insulation layer formed on the control gate.
According to a fourteenth aspect of the invention, there is provided the device of the sixth aspect, wherein the distance between the pair of first side faces is substantially equal to the width of the device region.
According to a fifteenth aspect of the invention, there is provided the device of the tenth aspect, wherein a plurality of stacked gates each having the floating gate and the control gate are formed on the semiconductor substrate, and the booster electrode is formed between adjacent two of the stacked gates.
According to a sixteenth aspect of the invention, there is provided the device of the tenth aspect, further comprising a plug for contact with a bit line, the plug being formed of the same conductive material as the booster electrode.
According to a seventeenth aspect of the invention, there is provided the device of the tenth aspect, further comprising a wiring formed of the same conductive material as the booster electrode.
According to an eighteenth aspect of the invention, there is provided the device of the tenth aspect, further comprising an insulation layer formed on the control gate.
According to a nineteenth aspect of the invention, there is provided the device of the tenth aspect, further comprising a device isolation insulation layer, formed on the semiconductor substrate, for defining a device region, wherein the distance between the first face and the second face of the floating gate is substantially equal to the width of the device region.
According to a twentieth aspect of the invention, there is provided the device of the nineteenth aspect, wherein the device isolation insulation layer is formed of an insulation material buried in a trench formed on the semiconductor substrate, the trench being self-aligned with the first face and the second face of the floating gate.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinbefore.